The present invention relates to a tristate buffer.
Shown in FIG. 1 is a logic circuit diagram of a typical tristate buffer.
In FIG. 1, an input signal INs is fed to an inverter INV20 via a signal input terminal IN. The output signal of the inverter INV20 is fed to an inverter INV21. A clock signal CLK and an enable signal EN are fed to a 2-input NAND gate 21. The output signal of the NAND gate 21 is fed to an inverter INV22. The output signals of the inverters INV21 and INV22 are fed to a 2-input NAND gate 22. The output signals of the inverters INV20 and INV22 are fed to a 2-input NAND gate 23. The output signal of the NAND gate 23 is fed to an inverter INV23. The output signal of the NAND gate 22 is fed to the gate of a P-channel MOS transistor P21 connected across a power supply terminal VDD and a signal output terminal OUT for generating an output signal OUTS. The output signal of the inverter INV23 is fed to the gate of an N-channel MOS transistor N21 connected across the signal output terminal OUT and a ground terminal GND.
Shown in FIG. 2 is a logic circuit diagram of another typical tristate buffer.
The tristate buffer of FIG. 2 is different from that shown in FIG. 1 in that it does not have an inverter for inverting an input signal, such as, the inverter INV20 shown in FIG. 1. An output signal /OUTs is generated at the signal output terminal OUT, which is an inverted signal of the output signal OUTs shown in FIG. 1. The sign xe2x80x9c/xe2x80x9d indicates logic inversion hereinafter.
The operation of the tristate buffer shown in FIG. 1 only is explained because that of the tristate buffer of FIG. 2 is almost the same.
The timing chart for signals on the tristate buffer (FIG. 1) is shown in FIG. 3.
The clock signal CLK having a period of T0 offers a pre-charging period to the tristate buffer while the signal CLK is in a L (low)-level state. The P-and N-channel MOS transistors P21 and N21 (the output stage) are off during the pre-charging period, thus the signal output terminal OUT having high impedance.
On the other hand, the clock signal CLK offers an evaluation period while it is in a H (high)-level state. The enable signal EN in a L-level state during the evaluation period makes the signal output terminal OUT continuously having high impedance.
The output signal OUTs goes to a H-level state when the input signal INs goes to a H-level state while the enable signal EN is in a H-level state. On the other hand, the output signal OUTs goes to a L-level state when the input signal INs goes to a L-level state while the enable signal EN is in the H-level state.
The tristate buffer must have a sufficient set-up time S0 for the input signal INs against a leading timing of the clock signal CLK. In other words, as shown in FIG. 3, a sufficient set-up time So should be provided for the input signal INs for the transition from an unstable state between H- and L-levels to a stable state in a H- or a low-level before the leading timing of the clock signal CLK.
Transition from the unstable to stable states behind the leading timing of the clock signal CLK would cause discharging at the signal out terminal OUT to bring the circuitry (not shown) connected to the terminal OUT into a malfunction.
The sooner the better for the tristate buffer to have a set-up time S0 for achieving a higher operating speed. When the output passage of the input signal INs from an input signal generator (not shown) is the critical path, an operation period of the input signal generator and the tristate buffer is obtained by addition of a period of generating the input signal INs and a set-up time S0. In other words, the sooner to have a set-up time S0, the higher the operating frequency.
The tristate buffer shown in FIG. 1 is, however, provided with two inverters (INV20 and INV21) connected in series between the signal input terminal IN and the 2-input NAND gate NAND22. The installation of such inverters causes a delay D0 for the output signal OUTs as shown in FIG. 3, thus having a slow operating speed.
In order to solve such a problem, the tristate buffer shown in FIG. 2 is provided with only one inverter INV21 between the signal input terminal IN and the 2-input NAND gate NAND22.
The tristate buffer (FIG. 2) is, however, put under load corresponding to P- and N-channel MOS transistors that constitute the inverter INV21 and also those constituting the 2-input NAND gate NAND23 when looked from the signal input IN.
This results in increase in load for the tristate buffer shown in FIG. 2 compared to that shown in FIG. 1, thus no increase in operating speed.
A purpose of the present invention is to provide a tristate buffer that operates at a high operating speed by reduction of load when looked from an signal input terminal to produce a small signal delay.
The present invention provides a tristate buffer including: a logic circuit to output a H (high)-level signal when H-level clock and enable signals are input thereto; a first P-channel MOS transistor having a source connected to a power supply terminal of the tristate buffer and a gate to which the output signal of the logic circuit is supplied; a second P-channel MOS transistor having a source connected to the power supply terminal and a gate to which the output signal of the logic circuit is supplied; a third P-channel MOS transistor having a source connected to the power supply terminal, a gate connected to a drain of the second P-channel MOS transistor, and a drain connected to a drain of the first P-channel MOS transistor; a fourth P-channel MOS transistor having a source connected to the power supply terminal, a gate connected to the drain of the first P-channel MOS transistor, and a drain connected to the drain of the second P-channel MOS transistor; a first N-channel MOS transistor having a drain connected to the drains of the first and the third P-channel MOS transistors and a gate to which the output signal of the logic circuit is supplied; a second N-channel MOS transistor having a drain connected to the drains of the second and the fourth P-channel MOS transistors and a gate to which the output signal of the logic circuit is supplied; a third N-channel MOS transistor connected between a source of the first N-channel MOS transistor and a ground terminal of the tristate buffer, a first input signal being fed to a gate of the third N-channel MOS transistor; a fourth N-channel MOS transistor connected between the source of the second N-channel MOS transistor and the ground terminal, a second input signal being fed to a gate of the fourth N-channel MOS transistor; an inverter having an input terminal connected to the drains of the first and the third P-channel MOS transistors and also the first N-channel MOS transistor; a fifth P-channel MOS transistor connected between the power supply terminal and an signal output terminal of the tristate buffer, a gate of the fifth P-channel MOS transistor being connected to the drains of the second and the fourth P-channel MOS transistors and also the second N-channel MOS transistor; and a fifth N-channel MOS transistor connected between the signal output terminal and the ground termial, an output signal of the inverter being fed to a gate of the fifth N-channel MOS transistor.
Moreover, the present invention provides a tristate buffer including: a logic circuit to output a H (high)-level signal when H-level clock and enable signals are input thereto; a first P-channel MOS transistor having a source connected to a power supply terminal of the tristate buffer and a gate to which the output signal of the logic circuit is supplied; a second P-channel MOS transistor having a source connected to the power supply terminal and a gate to which the output signal of the logic circuit is supplied; a third P-channel MOS transistor having a source connected to the power supply terminal, a gate connected to a drain of the second P-channel MOS transistor, and a drain connected to a drain of the first P-channel MOS transistor; a fourth P-channel MOS transistor having a source connected to the power supply node, a gate connected to the drain of the first P-channel MOS transistor, and a drain connected to the drain of the second P-channel MOS transistor; a first N-channel MOS transistor having a drain connected to the drains of the first and the third P-channel MOS transistors and a gate connected to the drains of the second and the fourth P-channel MOS transistors; a second N-channel MOS transistor having a drain connected to the drains of the second and the fourth P-channel MOS transistors and a gate connected to the drains of the first and the third P-channel MOS transistors; a third N-channel MOS transistor having a drain connected to a source of the first N-channel MOS transistor and a gate to which a first input signal is supplied; a fourth N-channel MOS transistor having a drain connected to a source of the second N-channel MOS transistor, a source connected to a source of the third N-channel MOS transistor, and a gate to which a second input signal is supplied; a fifth N-channel MOS transistor connected between the sources of the third and the fourth N-channel MOS transistors and the ground terminal, and a gate to which the output signal of the logic circuit is supplied; an inverter having an input terminal connected to the drains of the first and the third P-channel MOS transistors and also the drain of the first N-channel MOS transistor; a fifth P-channel MOS transistor connected between the power supply terminal and an signal output terminal of the tristate buffer, a gate of the fifth P-channel MOS transistor being connected to the drains of the second and the fourth P-channel MOS transistors and also the drain of the second N-channel MOS transistor; and a sixth N-channel MOS transistor connected between the signal output terminal and the ground termial, an output signal of the inverter being fed to a gate of the sixth N-channel MOS transistor.